High performance IIR filters for interpolation and decimation

Abstract This technical note looks at implementing high performance polyphase IIR filters with very low FPGA resource requirements. These structures have the property that order filters can be implemented with just multiplications. The filters can be shown to have low sensitivity to coefficient quantisation, leading to efficient implementation in fixed point. Furthermore the maximum gain at any node in a filter stage is bounded meaning that only 1 bit of headroom is required for intermediate calculations. A general architecture suitable for pipelining and mapping to Xilinx DSP slices is presented. Finally a number of multiplierless 5 and 10 order elliptic filter designs are presented which are applicable to efficient polyphase interpolation and decimation. The group delay variation can be minimised by adding all-pass equaliser sections.